Field of the Invention
Embodiments of the present invention relate generally to graphics processing and, more specifically, to managing deferred contexts in a cache tiling architecture.
Description of the Related Art
Some graphics subsystems implement a tiling architecture in which a render target is divided into partitions referred to as “tiles.” Some tile-based systems also store data in an on-chip cache memory during rendering, which increases performance and reduces memory bandwidth consumption. For improved performance, multiple processing entities also may be implemented to process the tiles in parallel.
In operation, graphics processing subsystems may be aware of a specific set of render targets to which rendering work may be written. In the case of a tiling architecture, the tiling unit may be configured with certain settings based on the set of render targets. When the set of render targets is modified, the tiling unit may be required to stop accepting new work and process completely all work previously received before accepting any new work. Consequently, if the set of render targets is modified too often, then the interruptions experienced by the tiling unit may contribute to wasted processing time and a loss of efficiency.
Deferred contexts are a mechanism included in the DirectX 3D version 11 application programming interface (API) specification by which an application program may record command lists for transmission to a device driver for playback to a graphics processing subsystem at a later time. Each command list is assumed to begin with a fully cleared graphics processing subsystem state. Thus, the DirectX 3D API sends commands to the device driver to clear the graphics processing subsystem state after replaying each command list. This mechanism helps to facilitate application-level parallelism by allowing multiple concurrently running execution threads to record command lists for later playback. However, this mechanism also transmits many state reset commands, such as commands to reset the set of the render targets, to the graphics processing subsystem. In a tiling architecture, such a large number of state reset commands may cause the tiling unit to be interrupted quite often, leading to overall decreased system performance.
As the foregoing illustrates, what is needed in the art is a technique for efficiently managing state changes associated with deferred contexts.